Hierarchically Elaborated Phased-Array Antenna Modules and Faster Beam Steering Method of Operation

ABSTRACT

A system substantially updates all the phase shifter values of a phased array antenna by using two “global writes” to update these parameters to all phased-array transformation circuits simultaneously via a serial bus. Antenna elements, each controlled by a phased-array transformation circuit, are individually configured to transform phase and gain according to a register array. The register array has a local register group and a central register group, the local registers physically placed close in proximity to RF chains which each correspond to an element of array antenna, whereby each set of local registers control an individual antenna element and a central register controlling overall beam steering function. Gain values are hierarchically distributed. The apparatus is configured to efficiently elaborate phase shift weights into a submodule of a phase array antenna system with low noise and bandwidth.

CROSS-REFERENCES TO RELATED APPLICATIONS

Applicants claim priority from provisional application 61/757,688Efficient Phase Shift Control Apparatus and Method for HierarchicallyDistributed Elaboration Within a Phased Array Antenna filed 28 Jan. 2013which is incorporated by reference in its entirety. The presentapplication is a division of Ser. No. 14/106,801 filed Dec. 15, 2013, acontinuation in part of application Ser. No. 13/959,542 filed Aug. 5,2013.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

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INCORPORATION-BY-REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISK OR ASA TEXT FILE VIA THE OFFICE ELECTRONIC FILING SYSTEM (EFS-WEB)

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STATEMENT REGARDING PRIOR DISCLOSURES BY THE INVENTOR OR A JOINTINVENTOR

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BACKGROUND OF THE INVENTION

1. Technical Field

The invention concerns a steerable beam antenna system using aphased-array of planar elements.

2. Background

A conventional phased-array antenna enables a highly directive antennabeam to be steered toward a single certain direction. The direction ofan antenna beam may be controlled by setting the phase shifts of each ofthe antenna elements in the array. However, to enable higher mobility,the phase shifts must be updated more quickly than conventionallypracticed. In addition, cost and space considerations eliminate theobvious deployment of parallel data buses. For sensitive RF circuits andinterconnection in an phased-array antenna, it is also necessary tosimplify and confine the amount of digital interconnection. Thus it canbe appreciated that what is needed is a more efficient way ofdissemination of the phase shift control information to a substantialnumber of phase shifters for an antenna array with a high number ofantenna elements and possibly more than one simultaneous target.

SUMMARY OF THE INVENTION

One aspect of the invention is a system which includes a processorcircuit for control over an antenna element array by generation of anfirst operand and a first global write command and a second operand anda second global write command; the processor coupled to a serial bus ona system printed circuit board which conductively transmits operands andcommands, the serial bus coupled to a plurality of phase-arraytransformation (PhAT) circuits, whereby the first operand is stored intoeach of the plurality of PhAT circuits substantially simultaneously andthe second operand is stored into each of the plurality of PhAT circuitssubstantially simultaneously wherein the operands are generated todirect a beam direction.

An efficient phase control scheme for a phased-array antenna consistingof a number of small submodules (subarrays) is disclosed. Each submodule(subarray) has a digital interface and contains a number of antennaelements and the associated phase shifters. The disclosed phase controlscheme requires dissemination of minimum amount of phase controlinformation to the submodules.

A serial bus is used to disseminate the phase shift control information.The serial bus has the advantages of simplicity and reduced volume,routing, and cost over a conventional parallel bus. This is especiallytrue for a phased-array antenna with high number of antenna elements.Minimizing the distribution of information enables a substantially lowerbus speed and cost.

An array of registers local to each antenna element of a phased-arrayantenna contains phase shifter and gain equalizer values. Receiving anaddress, position, or location within the register array from adirectional beam controller determines a beam direction. These valuescan be preloaded and a specific set of phase shifter and gain equalizervalues corresponding to a beam direction indicated by disseminating apointer. Alternatively, a digital functional logic circuit for eachantenna element can determine the required phase shift on the fly byreceiving a phase increment broadcast to every antenna element.

An apparatus is configured to efficiently elaborate phase shift weightsinto a submodule of a phased-array antenna system. Each subarray phasecontrol submodule is uniquely configured to receive and elaborateweights for a submodule of elements to control phase shifters. Majoroperators and minor operators are received and transformed by anapparatus coupled to a phased-array antenna suitable for a high mobilitydevice. Each submodule determines its own base phase shift weight perits unique configuration. A recursive adder or multiplier applies phaseincrements to direct an antenna beam by controlling elements within anarray subset.

A phased-array antenna panel is constructed from building blocks. Theseare a plurality of front end modules, mounted to a Printed Circuit Board(PCB). Each front end module has a plurality of antenna elements coupledto a frontend die. The frontend die is coupled to a phased-arrayprocessing die.

A customized and customizable Radio Frequency Integrated Circuit (RFIC)device includes: phased-array processing blocks; phase-shifters,combiners, splitters, gain equalizers, buffer amplifiers, and a digitalsignal control and interface circuit.

A register array in each RFIC is grouped into a local register group anda central register group, the local registers physically placed close inproximity to RF chains which each correspond to an element of arrayantenna, whereby each set of local registers control an individualantenna element and a central register controlling overall RFICfunction.

The system provides several choices for configuring the antenna array. Alookup method determines antenna element phase and gain settings fromstorage or a computation method determines antenna element phase andgain settings. They may be used separately or combined for corner cases.

The method of operation for the apparatus includes several alternativesexplicated below for controlling slave RFIC devices in an antenna array.The details of one or more embodiments of the invention are set forth inthe accompanying drawings and the detailed disclosure below. Otherfeatures, objects, and advantages of the invention will be apparent fromthe description and drawings, and from the claims.

BRIEF DESCRIPTION OF FIGURES

The purpose of the accompanying figures is to aid in the appreciation ofthe subject matter without clutter or limitation. While theillustrations of 2 by 2, 4 by 4, or 16 element modules are intended tosupport the understanding of the reader, it can be appreciated that thedisclosed economies are even greater for a much larger array of modulesand submodules. Thus the discussion and claims are not limited to thevalues or numbers of elements shown wherein:

FIG. 1 is system diagram of an antenna element array controlled by ahost processor; FIG. 2 is an electrical schematic of antenna elements,amplifiers, and a phase control circuit communicatively coupled; FIG. 3is a block diagram of a semiconductor device for frequency translationand phase control; FIG. 4 is a flowchart of method steps to operate aphase control circuit device; FIG. 5A is a radiating surface view of anarray of front end modules mounted on a phased-array antenna panel; FIG.5B is an edge or side view of an array of front end modules mounted on aphased-array antenna panel; FIG. 6 is a radiating surface view of theantenna elements of a plurality of front end modules mounted on aphased-array antenna panel; FIG. 7 is a schematic of a plurality ofphase control circuit devices electrically coupled via a serial bus toan Antenna Element Array Controller circuit; and FIG. 8A-D are partialblock diagrams of embodiments of a Phased-Array Transformation circuitwhich can be used as phase control circuit devices highlighting onlydistinguishing characteristics and not cluttered with repetition ofblocks common to all embodiments.

DETAILED DISCLOSURE OF EMBODIMENTS

A phased-array antenna panel is constructed from building blocks. Theseare a plurality of front end modules, where circuits and processing unitare embedded locally to process sensitive RF signal, within a main PANELPrinted Circuit Board (PCB). A phased-array antenna allows a highlydirective antenna beam to be steered toward a variable target directionin any mobile situation. The direction of the antenna beam is adjustedby resetting the phase shifts of the antenna elements. To enable highmobility, the phase shifts need to be updated quickly. Thus, Applicants'efficient way of dissemination of the phase shift control information tothe phase shifters of the antenna elements addresses a long sought need.

Each front end module has a plurality of antenna elements coupled to afrontend amplifier. In an embodiment these amplifiers use GaliumArsenide (GaAs) technology. The frontend die is coupled to aphased-array processing die in an embodiment economically manufacturedin CMOS. The antenna elements are embedded in the top of a substrate andthe frontend dies and the phased-array processing die are flip-chipmounted onto the bottom or top layer of substrate of each front endmodule. Input or output signals are conducted through the substrate tothe phased-array processing die and to passive combiners and splittersembedded in the PCB; and a transceiver die flip-chip mounted on thePANEL PCB whereby the antenna transmitted and received signals arefrequency translated.

The digital signal control and interface circuit has at least oneglobal/individual indicator pad and a plurality of individual dieaddress setting pads enabling a first die address to be configured at afirst location on the PCB which connects a plurality of die address padsto a first combination of logic high or logic low and a second dieaddress to be configured at a second location on the PCB which connectsa plurality of die address pads to a second combination of logic high orlogic low whereby registers within the RFIC are assigned uniqueaddresses.

Tying the front end modules together is a PCB comprising a data andaddress bus; a plurality of die address pads; and a global die selectionpad and a transfer format mode pad. In order to scale, a driver isdisclosed in an embodiment, which buffers the bus output; the buscoupling a microcontroller master device and coupling a plurality ofslave devices on each RFIC.

The method of operation for the apparatus includes several alternativesfor controlling slave RFIC devices in an antenna array. These includeinitializing common registers with calibrated gain values; storing phaseshifter values in local registers; computing phase shifter values; andlooking up gain settings.

To illustrate the scheme, consider an exemplary submodule of 4.times.4elements using 4 bit phase shifters for a planar array in twodimensions. The extension to three dimensional array is conceptuallystraightforward for those well versed in the art of phased array design.The extension from Cartesian to Spherical Coordinate for the elementlayout is also routine. For the purpose of simplicity we use the planarexample.

The phase increments required for pointing are .DELTA.x and .DELTA.y.Let the phase of element (0,0) be .phi..sub.00. Then

.phi..sub.xy=.phi..sub.00+x.DELTA.x+y.DELTA.y.

Multiplying a phase increment by an integer may be expensive in onetechnology and less significant in another implementation. The method ofthe invention is the multiplication of phase increments which have beendistributed to the submodules. In one preferred embodiment which avoidsliteral multiplication by integer, it can be computed recursively:

Compute first row: .phi..sub.x+1,0=.phi..sub.x0+.DELTA.x(3 adds)

Compute the next rows: .phi..sub.x,y+1=.phi..sub.x,y+.DELTA.y(12 adds)

To avoid quantization errors in the computation, the phases used incomputation are represented in finer increments, e.g. 6 bits. The exactnumber of bits enable embodiments to accommodate different qualityrequirements. After computation, the phases can be rounded off to lesserresolution. Advantageously, the non-conventional central controller(digital signal processor) of the phased-array antenna only needs tosend the .phi..sub.00, .DELTA.x, .DELTA.y to the submodule for eachsteering direction. In an illustrative embodiment, the number of bitsrequired per submodule is 3.times.6 bits. The number of additions is 15.

In one embodiment, wherein the number of submodule is large, a largevolume of phase control information would need to be disseminated to allthe submodules. A non-conventional second level of hierarchy isintroduced by this invention to enable massive scaling. If thesubmodules are arranged in the planar rectangular grid, each with i, jindices (e.g. 0, 1, 2, 3 . . . ) corresponding to the position in thetwo orthogonal axes, for the phased-array antenna, the initial phase.phi..sub.00[i,j] of the [i,j].sup.th submodule, is computed as follow.

.phi..sub.xy[i,j]=.phi..sub.00[i,j]+x.DELTA.x+y.DELTA.y.

.phi..sub.xy[i,j]=.phi..sub.00[0,0]+i.DELTA.x′+j.DELTA.y′+x.DELTA.x+y.DELTA.y.

In an embodiment, a set of fixed offsets (.phi..sub.fixed x,y[i,j]) areadded to the equation to account for any fixed phase offset (delay)offset for each antenna element in the implementation. And such fixedoffsets do not need to be updated every time and the .phi..sub.00[0,0]value can be absorbed into .phi..sub.fixed x,y[ij].

.phi..sub.xy[i,j]=.phi..sub.fixedx,y[i,j]+i.DELTA.x′+j.DELTA.y′+x.DELTA.x+y.DELTA.y.

The principle of operation of the invention is to multiply a phaseincrement by an integer. Embodiments of the invention may be moreexpensive in some technologies than in other embodiments of theinvention. In one preferred embodiment which avoids use of a multipliercircuit, phase increment is computed recursively:

Computing first row: .phi..sub.00[i+1,0]=.phi..sub.00[i,0]+.DELTA.x′

Computing the next rows:.phi..sub.0,0[i,j+1]=.phi..sub.0,0[i,j]+.DELTA.y′

Because the antenna steering remains unchanged if the phase shifts ofall antenna elements are added the same amount of phase shift, theinitial phase .phi..sub.00[0,0] can be set to zero. Therefore, the phasecontrol information, .DELTA.x, .DELTA.y, .DELTA.x′, .DELTA.y′, to bedisseminated to all the submodules is independent of the number ofsubmodules. This bears emphasis and elaboration. Even if the number ofsubmodules is 1024 or 512 instead of 16, there are only four operandswhich need to be disseminated to all of the submodules. The presentinvention is easily distinguished from conventional phased antenna arraycontrol by the substantially lower bandwidth requirement to distributephase information into the shift circuits. Both lower data rates andhigher phase data uploads are accomplished with less cost. The inventionreduces bus speed or increases beam direction change rapidity or both.

One preferred embodiment for realizing the indexing of submodules is toprovide address pins for the two orthogonal axes. Each address pin wouldbe tied to logic high or logic low based on the indices: i and j.

Referring now to the drawings, an apparatus embodiment of the inventionshown in FIG. 1 is a plurality of antenna elements 6000 communicativelycoupled to a host processor 1000 whereby phase increments or addresses,positions, or locations within an antenna weight vector table may bedistributed to every antenna element, wherein each antenna elementcomprises a phase shifter and gain equalizer coupled to a plurality oflocal registers which contain an antenna weight vector table.

FIG. 2 is an electrical schematic of a plurality of antenna elements201-216 which are electrically coupled to amplifiers 210-240. Eachamplifier is in turn coupled to a phase control circuit 300. In anembodiment, each phased-array processing circuit there are 16 RF chainsto process the signals for 16 antenna elements on the front end modules.In an embodiment, the on-chip registers are partitioned into 16 localregister groups ad one central register group, whereby the number ofdigital traces on the die or minimized. Each of the 16 register groupsis located in the corresponding RF chains.

FIG. 3 is a block diagram of a phase control circuit 300. In anembodiment, the semiconductor device has an additional transceiverfunctionality either from additional radio frequency circuits 370 orreuse of phase control circuits. The phase control circuit apparatuscomprises an operands receiver 330 coupled to an antenna weight valuefunction 350 which may be a multiplier or a recursive adder. The antennaweight value function 350 is further communicatively coupled to aconfiguration store 310. A plurality of X by Y phase shifters 391-399 isfurther coupled to the antenna weight value function. A plurality ofregisters receive the results and provide them to the antenna elements.

At minimum the configuration store is no more than the value of i andthe value of j representing the position of the subarray phase controlsubmodule within a flat rectangular grid. This may be accomplished by amemory, fuses, or pins tied to logic one or zero. In an embodiment, theconfiguration store further has a set of correction phase errors foreach antenna element or phase shifter.

In an embodiment, a single major operand is the base phase shift for asubmodule. In an embodiment, a pair of major operands is received andused in combination with the configuration stored data to determine abase phase shift for the entire submodule. In an embodiment, a pair ofminor operands is received and used as phase increments in determiningeach individual array element's phase shift weight.

Referring to FIG. 4, a method for operating an exemplary system such asillustrated in FIG. 3 is disclosed. Each submodule receives a pluralityof operands from a central controller 430. Advantageously, the disclosedsubject matter enables a low cost serial bus to disseminate the phaseshift control information. In an embodiment, only four operands arerequired and may be shared among many submodules. Each submodule haseither stored or hardwired a configuration which reflects its uniqueposition within an array. In an embodiment this is a value for i and avalue for j within a planar rectangular grid. An alternative embodimentcould use a polar coordinate system. Two of the operands distributed tomany or all of the submodules are major operands. One or both arerecursively added to determine and store a base phase shift for thesubmodule 440. In an embodiment the number of additions is related tothe values of i and j. Thus the determination of the base phase shiftfor each submodule is done in parallel at the submodule itself andcentral controller performs a broadcast transmission to many if not allsubmodules.

Each subarray phase control submodule 300 having determined its own basephase shift, the recursive adder then recursively adds a first minoroperand to the base phase shift to determine a phase shift weight foreach of a first plurality of shifters and stores the result 460. Thiscan be thought of as determining a phase weight vector for a row (or acolumn) by adding a phase increment once, twice, or thrice and so forthfor index 1, 2, 3, etc.

Each subarray phase control submodule 300 having determined a phaseweight vector, the recursive adder then recursively adds a second minoroperand to the stored phase shift weight of each plurality of shifters480. In other words the second phase increment is added once, twice, orthrice to the vector to determine phase shift weights for the fullarray.

Again, each submodule is operating in parallel with each other submoduleand only performing additions. In an embodiment, a multiplier canperform shifting if area and speed are improved but this is animplementation optimization. In an embodiment the major and minoroperands may be transmitted separately by the central controller or allin one transmission. In embodiments self-clocking may controlcomputation and storage and in another embodiment a clock.

FIG. 4 is a flowchart of method steps which when executed by a processoror micro controller or a circuit control the directionality of aplurality of antenna elements. Advantageously, configuration values maybe distributed to each front end module at each location duringnon-critical periods. Then during dynamic operation only major and minoroperands may be distributed in parallel operations and transformed todetermine phase shifts for each antenna element under the control of thecircuit.

A method of operation for a phase control circuit comprises receivingand storing configuration data which is distributed to each front endmodule 410.

In an embodiment, the phase shifters are reinitialized to place into aknown state in step 420.

In general the method, once initialized, is started by receivingoperands 430 from a central controller. These include both majoroperands and minor operands.

In step 440, the method includes recursively adding or multiplying majoroperands to determine submodule base shift per configuration and storinginto registers.

In step 480, the method includes recursively adding or multiplying asecond minor operand to determine a stored base shift weight of eachplurality of shifters. This step is repeated for all shifters and theresults stored into registers.

In an embodiment, needed error corrections may be determined in testingor maintenance and stored in configuration store. At step 490, in anembodiment, the method further comprises reading phase shift errorcorrection bias for each shifter from configuration store and adding toeach phase shift weight for all shifters and storing the result intoregisters.

Referring again to FIG. 4, in an embodiment, it may be advantageous toreinitialize the weights of the phase shifters prior to the previouslydisclosed steps 420. Or it may be sufficient to overwrite selected phaseshift weights as each one is determined. In an embodiment, themanufacture and assembly of the antenna array may determine the i and jindexing of each submodule of the array or they may be stored intoprogrammable memory 410. One embodiment for realizing the indexing ofsubmodules is to provide address pins for the two orthogonal axes. Eachaddress pin may be tied to a logic high or logic low based on theindices: i and j. Sockets for the submodules may be soldered into thesubstrate according to the indices. Even floating gates, wirebonding,switches or jumpers may be a cost effective embodiments. Resistive fusesmay be blown to tie address pads for each die to a unique address valueat each location on the PCB.

In an embodiment, a phase shift error correction bias is stored into theconfiguration for each shifter 410. To mitigate phase errors in theimplementation, a set of phase shift error correction bias values can beadded into a configuration store within each submodule, in anembodiment, during configuration 410. Optionally, in that embodiment, afurther process is to read phase shift error correction bas for eachshifter from configuration store and to add to each phase shift weightfor all shifters and to store 490.

In other words, to compensate the phase errors in the implementation, aset of correction phase errors .DELTA..phi..sub.xy can be pre-storedinside the registers within the submodules. The correction phase errors.DELTA..phi..sub.xy can be obtained via calibration procedure in the labor production process. The phase shift to be applied to each antennaelement would be .DELTA..phi..sub.xy+.phi..sub.xy. Note that.DELTA..phi..sub.xy does not change with different steering angles, butcould be a function of temperature and other factors.

In an embodiment the apparatus and method is extended into a 3dimensional phased-array which comprises operands .DELTA.x, .DELTA.y,.DELTA.z, .DELTA.x′, .DELTA.y′, .DELTA.z′.

For clarity of exposition, an illustrative non-limiting embodiment ofthe subject invention is first provided:

Each antenna element of a phased-array antenna has a local antennaweight vector table which contains phase shifter and gain equalizervalues. A beam controller transmits a location, position, or address ofa register in which the antenna weight vector table is stored to controleach antenna element. The antenna element further has a digitalfunctional logic circuit configured to generate required phase shiftsinto the registers of each element.

Two possible approaches for setting the phase shifter and gain equalizervalues in the RF chain are described first. In approach 1, thephased-array beam is formed by loading each antenna element withspecific phase shifter setting value (and gain equalizer setting value)from an antenna weight vector table. The antenna weight vector tablecontains a set of antenna weight vectors, in an embodiment, sixty-four(64). Each weight vector contains a set of phase shifter settings forall antenna elements. A table of phase shifter settings, (again e.g. 64)is stored in the local registers for each RF circuit chain correspondingto an antenna element. The antenna weight vector table consists of theselocal phase shifter registers. The values of phase shifter setting arepre-stored in the antenna weight vector table of each die and be usedfor pointing various beam directions, in this embodiment up to 64,typically, covering the vicinity of a particular beam direction indiscretely chosen settings. The resolution of these discretely settingsare chosen from system level study. Once the weight table is loaded, thehost processor only needs to select which position in the antenna weightvector table to be used for the phase shifters. A specific positionwithin the antenna weight vector table stores the antenna weightcorresponding to a beam direction. The preferred embodiment uses acommon register to store the address pointer of the position in theantenna weight vector table. The distribution of register addresses (viaaddress pointer) rather than conventional antenna weights improves theantenna beam transition movement speed within the beam directional rangecovered by the antenna weight vector table. Note that only a singleaddress pointer is disseminated for all the RFIC dies within thephased-array antenna for a beam direction.

However, when the beam direction is outside of the directional rangecovered by the stored antenna weight vector table, a new antenna weightvector table would need to be loaded. There might be some delay inloading the new table. This is especially true for a phased-arrayantenna with high number of antenna elements. To enable improved highermobility, the phase shifts need to be updated quickly. Thus, it can beappreciated that a more efficient dissemination of the phase shiftcontrol information to the phase shifters of the antenna elements isneeded.

Note that the antenna weight table values can be obtained throughcalibration of antenna beam in the laboratory. This allows correction ofany anomaly in the phase shifter and equalizer values.

We further disclose a second approach for fast loading of the phaseshifter setting by employing a plurality of digital functional logiccircuits to generate in parallel each required phase shift on-the-fly.In an embodiment wherein the antenna elements are placed linearly in a xand y directional rectangular grid on a plane, the phase shift of thecorner element (0,0) is represented as .phi..sub.00 and the phaseincrement in the required for x direction and y direction are .DELTA.xand .DELTA.y, respectively. The phase shift for the (n.sub.x, n.sub.y)element on the rectangular grid can be represented as

.phi..sub.xy=.phi..sub.00+n.sub.x.DELTA.x+n.sub.y.DELTA.y.

When the index (n.sub.x, n.sub.y) for the antenna element maps to theaddress of the registers, the invention provides that only the .DELTA.xand .DELTA.y needs to be passed to each digital functional logic circuitto determine the phase shift. Note that the phase shifter setting haslimited quantization. So, the actual phase shifter value for each(n.sub.x, n.sub.y) element is

Quan[.phi..sub.xy]=Quan[.phi..sub.00+n.sub.x.DELTA.x+n.sub.y.DELTA.y.]

Given that in actual silicon implementation, the phase shifter valuewill need to be corrected by some fixed offset .DELTA.n.sub.x, n.sub.y,the phase shifter value to be used should be

Quan[.phi..sub.xy]=Quan[.phi..sub.00+n.sub.x.DELTA.x+n.sub.y.DELTA..sub.y+.DELTA.n.sub.x,n.sub.y]

To generalize the subject matter of the invention, the applicationdiscloses two approaches for setting the phase shifter and gainequalizer values in the RF chain. In applicant's approach 1, thephased-array beam is formed by loading each antenna element withspecific phase shifter setting value (and gain equalizer setting value)from an antenna weight vector table. The antenna weight vector tablecontains a set of V antenna weight vectors. In an embodiment, theinteger value of V is within the range 16-512. However, as storagedensities continue to improve geometrically, the number of antennaweight vectors may be multiplied. Each weight vector contains a set ofphase shifter settings for all antenna elements. A table of V phaseshifter settings is stored in the local registers for each RF circuitchain corresponding to an antenna element. The antenna weight vectortable consists of these local phase shifter registers. The values ofphase shifter setting are pre-stored in the antenna weight vector tableof each die and be used for pointing up to V beam directions, typically,covering the vicinity of a particular beam direction in discretelychosen settings. The resolution of these discretely settings are chosenfrom system level study. Once the weight table is loaded, the hostprocessor only needs to select which position in the antenna weightvector table to be used for the phase shifters. The address pointer isused for the selection of position in the antenna weight vector table.Since all the RFIC dies are loaded with the antenna weight vector tablecorresponding to V beam directions, dissemination of a single addresspointer would update the beam direction. This speeds up the antenna beamtransition movement within the beam directional range covered by theantenna weight vector table.

However, when a desired beam direction is outside of the directionalrange covered by the stored antenna weight vector table, new antennaweight vector table values need to be loaded. Any delay in loading thenew table, especially for a phased-array antenna with high number ofantenna elements will degrade the useful mobility of the antenna. Thus,it can be appreciated that what is needed is a more efficientdissemination of the phase shift control information to the phaseshifters of the antenna elements. As mentioned above, the antenna weighttable values can be obtained through calibration of antenna beam in thelaboratory which allows correction of any anomaly in the phase shifterand equalizer values.

A second general approach for fast loading of the phase shifter settingis to employ a plurality of digital functional logic circuits togenerate the required phase shift values in parallel on-the-fly. In anembodiment wherein the antenna elements are placed linearly in an x, yand z orthogonal array the phase shift of the corner element (0,0,0) isrepresented as .phi..sub.000 and the phase increment in the required are.DELTA.x, .DELTA.y, and .DELTA.z, respectively. The phase shift for the(n.sub.x, n.sub.y) element on the rectangular grid can be represented as

.phi..sub.xyz=.phi..sub.000+n.sub.x.DELTA.x+n.sub.y.DELTA.y+n.sub.z.DELTA.z.

The index (n.sub.x, n.sub.y, n.sub.z) for the antenna element reflectsthe address of the registers. Note that the only the phase incrementsneed be broadcast to every digital functional logic circuit to generatethe phase shift. As before, the phase shifter setting has limitedquantization and will need to be corrected by some fixed offset in eachdimension.

The invention further comprises combining approaches 1 & 2. In acondition when the beam direction is outside of the directional rangecovered by the antenna weight vector table per approach 1, the newantenna table can be computed via approach 2 to minimize the datatransfer requirement between the central controller and the localmodules.

A method for operating a phased-array antenna has the steps: receivingfrom a host processor a position in an antenna weight vector table;reading phase shifter and gain equalizer values from said position inthe antenna weight vector table; and pointing a beam by controlling aphase shifter and gain equalizer according to said read values.

An other method for operating a phased-array antenna has the steps: atan antenna element of a phased-array antenna, receiving a phaseincrement for each orthogonal direction; determining a phase shift forthe antenna element according to its index and the phase shift of itscorner element; adding a fixed offset to correct the phase shifter valuefor an anomaly; and storing the phase shift into a position of anantenna weight vector table.

An apparatus embodiment of the invention is a plurality of antennaelements communicatively coupled to a host processor whereby phaseincrements or addresses, positions, or locations within an antennaweight vector table may be distributed to every antenna element, whereineach antenna element comprises a phase shifter and gain equalizercoupled to a plurality of local registers which contain an antennaweight vector table.

FIG. 5A shows a radiating surface view of a plurality of front endmodules 200 of a phased-array antenna panel apparatus 5000. In a detail,the antenna elements 201 . . . embedded in the top few layers of thesubstrate are illustrated. The antenna elements are electrically coupledthrough the substrate to amplifiers on the same or opposite surface ofthe substrate. In an embodiment these amplifiers use Galium Arsenide(GaAs) technology.

FIG. 5B shows an edge or side view of a phased-array antenna panelapparatus 5000. A heat spreader component 510 is mechanically andthermally coupled to a panel printed circuit board (PCB) 530. Atransceiver die, 300, flip-chip mounted on the panel PCD, receivessignals for transmission and reception. In an embodiment, thetransceiver performs frequency translation from Ka-band to L-band, andfrom L-band to Ka-band. In an embodiment the transceiver die isthermally coupled to the heat spreader component but electricallycoupled through the panel PCB to a plurality of signal circuits and to aplurality of front end modules 200. Electrically conductive fasteners570 in an embodiment solder balls couple each front end module 200 to aunique location on the panel PCB. The presence or absence ofelectrically conductive fasteners 570 provides address information whichuniquely configures each of the front end modules for data reception andtransmission on an electrical bus. In an embodiment, the panel PCBprovides a connection to ground or to a logic value to provide anaddress value to each front end modules at each location. A RadioFrequency integrated circuit (RFIC) die consists of phased-arrayprocessing blocks which includes phase-shifters, combiners, splitters,gain equalizers, buffer amplifiers, digital signal control and interfacecircuits. In an embodiment, the RFIC also includes a transceiver tofrequency translate from a first band to a second band and from thesecond band to the first band. In an embodiment the radio frequencyamplifiers 210-240 and the phased-array processing dies 300 areflip-chip mounted onto the bottom layer of substrate in the front endmodule 200.

FIG. 6 is one view of an exemplary radiating surface of a phased-arrayantenna panel 6000 which contain a plurality of antenna elements e.g.201. One embodiment is a planar Cartesian or x-y arrangement of frontend modules. Other embodiments could be a polar coordinate arrangement,or a curved or faceted shape. Other manufacturing considerations mayenable square, rectangular, hexagonal, pentagonal, octagonal, or roundtiles for the antenna elements. The antenna elements may be disposed ina convex, concave, or parabolic 2d or 3d surface. The surface may beflexible and dynamic because the phase shifting can correct fortranslation, orientation, and attitude.

FIG. 7 is a schematic diagram 700 of a first Antenna Element ArrayController 710 coupled by at least one First Serial Bus 720 to aplurality of Phased-Array Transformation circuits 731-739. Each of theplurality of Phased-Array Transformation circuits is manufactured with aplurality of die address pads 741-749 which when uniquely bonded to alocation on a panel circuit board provides a unique address according tothe location (i, j) at which it is bonded. Each of the plurality ofPhased-Array Transformation circuits receives Antenna Element ControlValues on a serial bus adapter 751-759 coupled to the First Serial Bus.Each of the plurality of Phased-Array Transformation circuits operateson its received Antenna Element Control Values to provide a plurality ofAntenna Weight Values which transform the radio frequency signalstransmitted from or received by one of a plurality of antenna elements.

FIG. 8 are block diagrams of various embodiments of Phased-ArrayTransformation (PhAT) circuits which receive parameters from a serialbus and provide Antenna Weight Values (AWR) to elements of an AntennaElement Array. FIG. 8A illustrates a Phased-Array Transformation circuit800 with a non-transient parameter store 810 in which are antenna weightvalues which have stored during test, manufacturing, installation,tuning, or off-line maintenance. The Antenna Element Control Valuereceived off the serial bus may be an address in the non-transientparameter store where the antenna weight value to be used is alreadystored.

FIG. 8B illustrates a Phased-Array Transformation circuit 800 with anon-transient parameter store 810 and an antenna weight valuecomputation circuit 820. The Antenna Element Control Value received offthe serial bus may be operands to determine a base antenna weight of oneantenna element and the non-transient parameter store may contain anadjustment for each incremental i and each incremental j of the antennaelement array.

FIG. 8C illustrates a Phased-Array Transformation circuit 800 with anon-transient parameter store 810, an antenna weight value computationcircuit 820, and an antenna weight cache store 830. The Antenna ElementControl Value received off the serial bus may be an index into theantenna weight cache store for a previously computed set of antennaweights. This embodiment requires that the Antenna Element ArrayController track previously transmitted operands and determine an indexinto the antenna weight cache store.

FIG. 8D illustrates a Phased-Array Transformation circuit 800 with anon-transient parameter store 810, an antenna weight value computationcircuit 820, an antenna weight store 840 addressable by operand hashes,and a circuit to write to and read from the antenna weight storeaccording to operand hashes.

In an embodiment, the method includes having previously stored thecondition that the antenna is currently operating in a given region R,the host processor determines the region that the antenna will bepointing next R+1; the host processor determines that the region isadequately covered by one of the set of d phase weights previouslyassociated with d directions for each element according to a contentaddressable memory store device wherein the phase weights are computedusing the element index and the Submodule index:

For each submodule of 4.times.4 elements using 4 bit phase shifters, theelements indexed as follows: the phase increments required for pointingare .DELTA.x and .DELTA.y; set the phase of element (0,0) to be .phi.00and .phi.xy=.phi.00+x.DELTA.x+y.DELTA.y; as the submodules are arrangedin the planar rectangular grid, each with i, j indices corresponding tothe position in the two orthogonal axes, for the phased-array antenna,the initial phase .phi.00[i,j] of the [i,j]th submodule, is computed as.phi.xy[i,j]=.phi.00[i,j]+x.DELTA.x+y.DELTA.y and.phi.xy[i,j]=.phi.00[0,0]+i.DELTA.x′+j.DELTA.y′+x.DELTA.x+y.DELTA.y; thehost processor transmits to the Submodules an instruction to load phaseweight set d=5 (for example) to the phase shifters on the condition thatthe phase weight set for direction d has not been overwritten at eachsubmodule.

An apparatus embodiment of the invention further includes a functionaldigital logic circuit coupled to the phase shifter, the gain equalizer,and the plurality of local registers configured to receive one or morephase increment, determine a phase shift for the antenna element,correct the phase shift by a fixed offset, and store into a location ofan antenna weight vector table or load the antenna element with theresulting phase shifter setting value and gain equalizer setting value.

One aspect of the invention is a phased-array antenna panel whichcontains a number of frontend modules, embedded onto the main PCB (i.e.the PANEL PCB) of the panel. Each frontend module contains a certainnumber of embedded antenna elements, GaAs frontend dies, and CMOSphased-array processing die(s). The antenna elements are embedded in thetop few layers of the substrate and both the GaAs dies and the CMOS dieare flip-chip mounted onto the bottom layer of substrate in the frontendmodule. The input or output signals of the frontend modules can beeither actively processed (combining, splitting, and buffering of thereceived and transmitted signals) with the CMOS phased-array processingdies or passively processed (combining, splitting) with passivecombiners and splitters embedded in the PANEL PCB.

Another aspect of the invention is a Radio Frequency Integrated Circuit(RFIC) device which includes: phased-array processing blocks;phase-shifters, combiners, splitters, gain equalizers, bufferamplifiers, and a digital signal control and interface circuit; whichinterface circuit has at least one global/individual indicator pad and aplurality of individual die address setting pads enabling a first dieaddress to be configured at a first location on the PCB which connects aplurality of die address pads to a first combination of logic high orlogic low and a second die address to be configured at a second locationon the PCB which connects a plurality of die address pads to a secondcombination of logic high or logic low whereby registers within the RFICare assigned unique addresses.

The best mode of the invention has a PCB with a data and address bus, aplurality of address pads, a global selection pad, and a transfer formatmode pad.

In an embodiment for improved scaling the apparatus has a driver tobuffer the bus output; the bus coupling a microcontroller master deviceand coupling a plurality of slave devices on each RFIC.

Another aspect of the invention is a method for operation of theinvention which offers a plurality of methods including a lookup methodfor determining antenna element phase and gain settings; a computationmethod for determining antenna element phase and gain settings.

The method of operation for controlling phase control devices in anantenna array includes: initializing common registers with calibratedgain values; storing phase shifter values in local registers; computingphase shifter values; and looking up gain settings.

In an embodiment the method includes: controlling slave RFIC devices inan antenna array further by: initializing at the same time all commonregisters within every slave RFIC device in the antenna array to thesame calibrated gain values; transferring said calibrated gain valuesinto every instance of local registers for transformation by antennaelement specific phase shifter factors; storing antenna element specificphase shifter factors values in local registers; computing phase shiftervalues; and looking up gain settings.

Finally, a transceiver die, flip-chip mounted on the PANEL PCB, performsthe frequency translation from Ka-band to L-band for the receive signaland from L-band to Ka-band for the transmitted signal. Note that allactive phased-array processing shall use the same Phased-arrayTransformation circuit configured with different gain settings.

The PANEL PCB with the attached frontend modules and flip-chip(s)constitute the phased-array antenna panel.

In an embodiment, the digital module includes Digital control interfaceand registers, Digital functional logic circuit, and Data and AddressBus.

The digital control interface provides the digital interface and theregisters. To distinguish among many phase control devices on the Panel,the phase control device has in an embodiment, one global/individualindicator pad and 5 individual die address setting pads foraccommodating global or individual die write operation and up to 32unique device addresses.

While conventional configuration and control of antenna elements aredone through registers connected to analog circuits, this wouldintroduce noise, power consumption, and wasted area. In order to scaleand to reduce cost and size, each phase control circuit obtains itsaddress as follows. The address for each device is accomplished by using5 external I/O address pins (pads) in the device which are connected tologic high (VCC) or logic Low (GND) in a unique way in the Panel PCB toset the device address. (Note that the pads are connected to BGA ballson the frontend modules and then connectors to the resistors on PCB.)Depending on how many registers within each die, the registers areassigned unique addresses within the chip. The host processor can accessthe registers in each CMOS die by writing to or reading from thecorresponding unique CMOS die address/register address.

The PCB onto which the modules are mounted provides additionaldistinguishing characteristics.

Data and Address Bus provides the interface between all RFIC5 and themain processor/microcontroller. Since there are a large number of RFIC5in the system, the main processor needs to drive a large number ofRFIC5.

One aspect of the invention is a method for control of a Phased-ArrayTransformation circuit with a non-transient parameter store in which areantenna weight values which have stored during test, manufacturing,installation, tuning, or off-line maintenance, method comprising for arange of antenna beam directions, receiving an Antenna Element ControlValue off the serial bus which is an address in the non-transientparameter store where the antenna weight values to be used werepreviously stored; retrieving the antenna weight value for each antennaelement; and transforming the signals transmitted from or received byeach antenna element.

In an embodiment the method further includes, on the condition that adesired beam direction not within the range of beam directions for whichantenna weight values were previously stored in the non-transientparameter store, operating the Phased-Array Transformation circuit withan antenna weight value computation circuit by receiving an AntennaElement Control Value off the serial bus which are operands to determinea base antenna weight of one antenna element and reading thenon-transient parameter store for an adjustment for each incremental iand each incremental j of the antenna element array.

In an embodiment the method further includes operating a Phased-ArrayTransformation circuit with a non-transient parameter store, an antennaweight value computation circuit, and an antenna weight cache store, onthe condition the Antenna Element Array Controller tracks previouslytransmitted operands and determine an index into the antenna weightcache store, the method comprising receiving an Antenna Element ControlValue off the serial bus which is an index into the antenna weight cachestore for a previously computed set of antenna weights; retrieving theantenna weight value for each antenna element from cache; andtransforming the signals transmitted from or received by each antennaelement.

In an embodiment the method further includes operating a Phased-ArrayTransformation circuit with a non-transient parameter store, an antennaweight value computation circuit, an antenna weight store addressable byoperand hashes, and a circuit to write to and read from the antennaweight store according to operand hashes, on the condition that theAntenna Element Array Controller computes and transmits a hash ofoperands before transmitting the operands, the method comprising:receiving a hash of an operand, determining if antenna weight values arestored at the location of the antenna weight store corresponding to thehash; reading the antenna weight values; transforming signals with theantenna weight value; and otherwise proceeding to compute antenna weightvalues if not stored at the location corresponding to the hash.

As is known, there are three formats of SSI bus available on the hostprocessor. For the Freescale SSI formats, the clock polarity bit (SPO)is set to low for the steady (idle) state of logical low on clock lineand the phase control bit (SPH) is set to low for the data latching onthe first clock edge. As is known to those skilled in the art, the startof transmission is signified by the SSIFss master signal being drivenLow, causing slave data to be enabled onto the SSIRx input line of themaster. The master SSITx output pad is enabled.

One half SSIClk period later, valid master data is transferred to theSSITx pin. Once both the master and slave data have been set, the SSIClkmaster clock pin goes High after one additional half SSIClk period. Thedata is now captured on the rising and propagated on the falling edgesof the SSIClk signal.

In the case of a single word transmission, after all bits of the dataword have been transferred, the SSIFss line is returned to its idle Highstate one SSIClk period after the last bit has been captured.

However, in the case of continuous back-to-back transmissions, theSSIFss signal must be pulsed High between each data word transferbecause the slave select pin freezes the data in its serial peripheralregister and does not allow it to be altered if the SPH bit is clear.Therefore, the master device must raise the SSIFss pin of the slavedevice between each data transfer to enable the serial peripheral datawrite. On completion of the continuous transfer, the SSIFss pin isreturned to its idle state one SSIClk period after the last bit has beencaptured.

In embodiments, the SSIClk clock phase from the host process is slightlydifferent in the single transfer mode versus continuous transfer mode.In the continuous transfer mode, the SSIClk clock phase is delayed byhalf a clock cycle at the beginning of each transfer cycle. So, theSSIClk clock phase is not continuous across the transfer cycles. Thisformat is different from TI synchronous serial format which hascontinuous SSIClk clock phase and is slightly faster. By thisdisclosure, Applicant intends illustration of constructive reduction topractice of the invention in either embodiment.

As is known to those skilled in the art, both Freescale and TI formatsare designed for full duplex data transfer using FIFO. Unanticipated inconventional practice, Applicants adopt a half-duplex byte read/writeformat as follows. In the write operation, the first 7 bits are theregister address, the 8th bit is the write or read (Write=1, read=0),the last 8 bits are the data byte.

In the read operation, the first 7 bits are the register address, the8th bit is the read (read=0), the last 8 bits are the data byte. Thefollowing timing diagram shows the Freescale format. For TI format, thedata is latched at the falling edge.

In an embodiment, a 7 bit address accommodates up to 128 registers. Inan embodiment, the on-chip registers are organized in multiple banks of128 registers. The selection of the register bank is done throughsetting the RB_CONFIG register. Detailed description will be provided inthe later section.

In an embodiment, there are 5-31 external input pads (DIE_ADD) to acceptthe die address from host processor. If the 5 input matches the dieaddress, the die is selected for read/write operation. An additionalinput pad (GI_SEL) is used for global or individual die selection. Ifthe global/individual die selection input is high, it is a globalsetting and all dies shall accept the SSI signal. If theglobal/individual die selection input is low, only the individual diewith die address match shall accept the SSI signal. As shown on theright side of die, the 5 pads are connected to Logic high or Logic lowto set the die address. The Freescale/TI pad selects which format to beused. Note that the digital design shall support Freescale frame formats(SPO=0, SPH=0) for both the single or continuous transfer mode and theTI synchronous serial mode.

In a presently preferred embodiment, the apparatus connects serial SSIbus to up to 32 dies in parallel. The parasitics of large number offan-outs might affect the bus speed. In an embodiment, external linedrivers such as 74HTC244 buffer the SPI bus to drive large fan out.Multiple layers of buffering using line drivers might be required. It isadvisable to include bus driver and bypass jumper using chip resistor inthe final PCB design to enhance the reliability of the design. Thedecision to include bus driver or not are embodiments.

SPI bus supports the master or slave device. The SPI Master provides theSPI clock and the control of the bus direction. The host processor isthe SPI master and all phase control circuits shall be SPI slaves. Allphase control circuits will have unique SPI address which is configuredthrough resistors on PCB connected to the I/O pads of the frontendmodules. The address of the frontend module will be set according topre-determined order which allows fast antenna weight vector update. Thetarget SPI bus write speed is 25 MHz when 16 slave dies are connected toa master. The SPI bus speed will be decided after the initial testing.The maximum read speed of SPI bus is 12.5 MHz.

In an embodiment, the candidate microcontroller is TI's ARM Cortex-M4core based Stellaris processor with maximum speed up to 80 MHz. TheLM4F230H5QR contains 4 SPI ports on-chip, each allows up to 8 16 bitvalues to be stored independently in both transmit and receive modes inthe 8-locations deep FIFO. Other microcontrollers are substantiallyequivalent.

For 48 dies on the Panel PCB, each SPI port can communicate with12.about.16 dies. Note that the SPI bus can operate at a maximum of 25MHz write speed. With 16 bit data registers, the read/write is about 1MHz.

Write Operation

When host processor writes to the SPI bus, all the dies connected to thesame bus simultaneously receive the data. For individual die write(GI_SEL=0), the die with an address match (Die_ADD) shall accept thedata into the register. To be precise, when the Die_ADD bits matches thedie address (determined by the pad connections), an internal chip selectis generated to allow further address decoding and the local registermatching the address accepts the data into register.

Read Operation

The host processor reads from the SPI bus. All the data_out pad of thedevice shall be initially in the high impedance tri-state. Once thefirst 5 address bit matches the die address, the data_out pad wouldbecome active. Once the read operation is complete, the data_out padwould return to high impedance tri-state.

Since the phase control devices contain lots of radio frequency (RF)circuits, it is extremely important to reduce the digital traces goingthrough the device. Parasitic coupling with the RF traces would affectthe performance of the RF circuit. Keeping the global digital traceswithin each phase control to a limited number which go through somepre-planned area only, such as underneath the passive RF combiners (RFcombiner only uses the top 2 layers of the metal) of each RF chain isthe best mode.

In a preferred embodiment, registers in each phase control circuit aregrouped into local registers and central registers, based on where theyreside within the die as shown in the diagram where (n=16). The centralregisters control the overall RFIC functions and the local registers,which are physically placed in close proximity to the local circuit (RFchains) blocks they control. In the phase control circuit, there aremultiple RF chains corresponding to the elements of array antenna, eachset of the local registers controls the RF circuit chain correspondingto individual antenna element and the set of central registers controlsthe overall phase control function.

Common Registers

A small subset of local registers, i.e. the common registers, containsidentical values for all RF chains. The values of the sets of commonregisters are duplicated in all RF chains and also in the central areaas well. The corresponding common registers are arranged in the sameorder in all RF chains and the central area. The corresponding commonregisters in all sets are assigned the same address.

Writing to Common Registers

The corresponding common registers in all sets is written with a singlewrite operation to the die when only one beam is desired. This reducesthe time required to configure all corresponding registers to enablehigh speed system operation. The sole purpose of the common registers isto speed up the write operation. Instead of writing to 16 localnon-common registers, a single write would set the 16 correspondingcommon registers.

Reading from Common Registers

In an embodiment, when the host processor reads a common registeraddress, only one set of physical common register (i.e., global commonregister set) within the die shall respond to the read operation andoutput the register value. All the other sets shall be read-disabled.This avoids the bus contention during read operation of the commonregisters.

Non-Common Central Register and Non-Common Local Register

In contrast, the set of non-common central registers controlling thecentralized circuits are not duplicated in the RF chains. The set ofnon-common local registers controlling the local circuits and are notduplicated in other RF chains and the central area.

SPI Bus within the Device

By partitioning registers into central and local registers, only asingle global data and address bus within a device is required. Theaddress decoders are duplicated in each RF chain. No other traces exceptfor SPI bus shall connect the central registers to a local circuits orlocal register to a central circuit. This reduces the number of globalinterconnection traces. Local registers should be placed carefully bythe local circuits to minimize crossing of digital traces through RFcircuits. As a guideline, the set of local registers and address decodershould be placed on the same relative location of all the local RFcircuits so that interconnections can be routed properly. The local andcentral registers are defined in this specification.

In an embodiment, only 7 address bits are available for accessingregisters within the die, accordingly, the registers are grouped todifferent banks of registers, each bank contains a maximum of 128registers. At any time, only one bank of register is active. This isconfigured via the TBD1 bits within a configuration register (RB_CONFIG)within the set of the common registers. At the power up, the RB_CONFIGis defaulted to zero and a default set of bank 0 registers is active.When the TBD1 bits in the RB_CONFIG is set to a value other than zero, adifferent bank of registers becomes active. This allows the maximumnumber of addressable registers to be TBD2.times.128 (where TBD2 is thenumber of register banks, note that 2 (TBD1−1) TBD2<2 TBD1). The addressof the RB_CONFIG register shall not be re-used at different banks.Physically, there shall be only one RB-CONFIG register in each set ofcommon registers.

Most of the RFIC functions are controlled by the Digital ControlInterface Circuit. Digital Function Logic Circuit will be needed toprovide the control of the phase shifter/gain equalizer. Two approaches(Approach 1 and Approach 2) for setting the phase shifter and gainequalizer values in the RF chain are to be implemented. Theimplementation shall allow independent operation of each approachconfigured by setting a central register. Each approach should befunctional when the digital logics implementing the other approach isremoved from the production chip.

In an embodiment, the digital function logic circuit is duplicated ineach RF chain.

Approach I (Table Lookup)

In approach 1, the phased-array beam is formed by loading each antennaelement with specific phase shifter setting value and gain equalizersetting value from an antenna weight vector table. The antenna weightvector table contains a set of TBD3 antenna weight vectors. Each weightvector contains a set of phase shifter/gain equalizer settings for allantenna elements. A table of TBD3 phase shifter/gain equalizer settingsis stored in the local registers for each RF circuit chain correspondingto an antenna element. The antenna weight vector table consists of theselocal phase shifter/gain equalizer registers. The values of phaseshifter setting are pre-stored in the antenna weight vector table ofeach die and be used for pointing up to TBD3 beam directions. Once theweight table is loaded, the host processor only needs to select whichposition in the antenna weight vector table to be used for the phaseshifters. This should be accomplished by a single write to the die. Thisspeeds up the antenna beam transition movement within the beamdirectional range covered by the antenna weight vector table. However,when the beam direction is outside of the directional range covered bythe antenna weight vector table, new antenna weight vector table need tobe loaded. There might be some delay in loading the new table. This isespecially true for a phased-array antenna with high number of antennaelements. To enable high mobility, the phase shifts need to be updatedquickly. Thus, an efficient way of dissemination of the phase shiftcontrol information to the phase shifters of the antenna elements areimportant. In an embodiment we disclose 2 AWV tables—one table will beused for immediate phase shifter/gain equalizer settings for each RFcircuit chain based on the AWV pointer and another AWV table will beused for future phase shifter/gain equalizer settings. The future tablecan be updated independently of the immediate table. The two tables canthen be ping-ponged by an appropriate index.

Note that the antenna weight vector (AWV) table shall be in the localregisters. Each AWV contains 16 registers for the 16 RF chains with thesame local address (LSB). Note that phase-equalizer values stored insidethe registers in RF chain need not be the same. Different values can beloaded into different RF chains to account for any discrepancies of thephase shifter/gain equalizer at different RF chains. The differentvalues are obtained through lab calibration of the phased-array antenna.

Loading Up and Phase Shifter/Gain Equalizer Value

To load up the proper antenna weight within the antenna weight vector,the apparatus provides a pointer for selection of one of the TBD3registers within the local registers. Note that the pointer resides in aregister AWV_POINTER within the common registers. Each time a value iswritten into the common register, it points to a specific AWV registerwithin the AWV table. Depending on the implementation, the specificregister being pointed either directly control the phase and gainequalizer (via a multiplexer controlled by the AWV_POINTER) in oneimplementation or in an alternate implementation, the value of thespecific register is copied onto (read out to) a latch located at thephase shifter/gain equalizer upon each write operation into theAWV_POINTER.

Approach II (Computation)

A second approach for fast loading of the phase shifter setting is toemploy digital functional logic circuit to determine the required phaseshift on-the-fly. Assuming the antenna elements are placed linearly in ax and y directional rectangular grid on a receiving device. Let thephase shift of the corner element (0,0) be .phi.00 and the phaseincrement for x direction and y direction are .DELTA.X and .DELTA.Y,respectively, for each frontend module, and phase increment for xdirection and y direction are .DELTA.x and .DELTA.y, respectively, foreach element within the frontend module. The phase shift for the (nx,ny) antenna element in the (mx, my) frontend module on the rectangulargrid can be represented as

.phi.xy=.phi.00+mx.DELTA.+my.DELTA.Y+nx.DELTA.x+ny.DELTA.y   (Equation1)

This allows different frontend module-to-frontend module spacing fromthe element-to-element spacing within the frontend module. Note that mx,my, .DELTA.X, .DELTA.Y, nx, ny, .DELTA.x, and .DELTA.y are needed in thedigital functional logic circuit to generate the phase shift. The nx andny corresponds to the RF chain index within each transformation circuit.For a transformation circuit controlling 4.times.4 antenna element, nxand ny takes on the value from the set of [0, 1, 2, 3].

In an embodiment, the phase shifter setting has limited resolution (4bits). So, the actual phase shifter value for the (mx, my, nx, ny)element is

Quan[.phi.xy]=Quan[.phi.00+mx.DELTA.X+my.DELTA.Y+nx.DELTA.x+ny.DELTA.y]  (Equation2)

In an embodiment, the on-the-fly phase shifter value computation isaccomplished by digital functional logic circuit. In an embodiment, 8bits (resolution=360/256 degree) is used to represent the values.phi.00, .DELTA.X, .DELTA.Y, .DELTA.x, .DELTA.y to yield high precisioncomputation. The computation of Equation 1 is with modulo 8 bitarithmetic in that embodiment.

In an embodiment, the phase shifter value is represented in thefractional value of 360 degree.

TABLE-US-00001 Integer Phase shifter Fraction Representation 0 degree0/360=0/16 0000 22.5 degree 22.5/360=1/16 0001 45 degree 45/360=2/160010 . . . 337.5 degree 337.5/360=15/16 1111

In an embodiment, all values are modulo 360 degree, i.e., all integerportion of the fractional representation shall be set to zero after eachoperation.

The Quan[.] function is used to round-up the resulting arithmetic intothe length of phase shifter bits as well as the modulo operation.Mathematically, the following operation is performed by circuits

1. Compute .phi.00+mx.DELTA.X+my.DELTA.Y+nx.DELTA.x+ny.DELTA.y usingmodulo 8 bit integer arithmetic (dropping carry bits)

2. Select 4 MSBs as the phase shifter value

Here mx, my, .DELTA.X, .DELTA.Y, .DELTA.x, and .DELTA.y are stored inthe common registers. The values of nx and ny are stored in localregisters. For each AWV update of the whole phased-array, only .DELTA.X,.DELTA.Y, .DELTA.x, and .DELTA.y are changed. mx, my, nx and ny arewritten once only during configuration stage.

AWV Setting

In approach 1, to write AWV_POINTER (common register) to multiple diessimultaneously, global write operation (GI_SEL=1) is used. Similarly, inapproach 2, when global write operation is used to write .DELTA.X,.DELTA.Y, .DELTA.x, .DELTA.y.

Note that approach 1 or approach 2 is selected via B1 in RB_CONFIG.

Gain Equalization Setting

In an embodiment, the antenna weight table values are obtained throughcalibration of antenna beam in the laboratory. This allows correction ofan anomaly in the phase shifter and equalizer values. Since the gainsetting for each phase shifter setting for a given element is based oncalibration and do not change (except maybe for large temperatureswing), it can be pre-loaded into the RF module during initialization,thereby reducing real time data transfer throughput. For approach 2,there are 16 gain register settings for the 4 bit phase shiftersettings. For approach 2, the gain equalizer values shall be stored in a16 element lookup table (each Gain Equalizer is TBD4 bits), in which theinput address is the phase shifter value and output correspondscalibrated gain setting for each phase shift. The 16 registers in thelookup table are local registers.

Quan[.phi.xy]--/-->16.times.1 Lookup Table->Gain equalizer value

AWV from Approach 2 (Computational Mode)

Method Embodiments

The RFIC digital module is coupled with the PCB microcontroller SPImaster via one of the SPI frame format as slave. Each SSI master willcontrol 12 (TBR) slave RFIC digital circuits.

There are 4 modes of system operation: [0141] Mode 1 (Initialization).In this mode the digital module is initialized and the data received bythe die will be destined for the Global and Local Registers. [0142] Mode2 (Read Back). In this mode, the data from the Global and LocalRegisters in the die with the die address match is read by the SPImaster. [0143] Mode 3 (Table Execute). In this mode, the phaseshifter/gain equalizer index is received by the AWV_POINTER register.[0144] Mode 4 (Compute). In this mode, .DELTA.X, .DELTA.Y, .DELTA.x, and.DELTA.y needed for Approach 2 are received by the Digital Module.

Initialization

The digital module accepts the data from the microcontroller and loadinto the local common registers of appropriate antenna elements thecalibrated gain values.

Read Back Mode

Upon command by the SPI master, the Digital Module sends the contents ofall registers to the SPI master.

Tabulation Mode

The tabulation mode embodiment is set by the B1 bit of RB_CONFIGregister. The Digital Module shall accept the data from the SPI masterand load into the common local registers the phase vector table. Uponcommand from the SPI master, the Digital Module loads the phase shiftervalues into the appropriate local registers. The Digital Module looks upthe gain settings for the associated phase shifter value into the localregisters.

Computation Mode

The computation mode embodiment is set by the B1 bit of RB_CONFIGregister. The Digital Module accepts the data from the SPI master andload into the Global and common local registers the constants. TheDigital Module computes the phase shifter values per (Equation 2) andload the result into the appropriate local registers. The Digital Modulelooks up the gain settings for the associated phase shifter value intothe local registers.

Phased-array antenna elements are placed linearly in a x and ydirectional rectangular grid on a receiving device. Let the phase shiftof the corner element (0,0) be .phi.00 and the phase increment for xdirection and y direction are .DELTA.X and .DELTA.Y, respectively, foreach frontend module, and phase increment for x direction and ydirection are .DELTA.x and .DELTA.y, respectively, for each elementwithin the frontend module. This allows different frontendmodule-to-frontend module spacing from the element-to-element spacingwithin the frontend module. Note that mx, my, .DELTA.X, .DELTA.Y, nx,ny, .DELTA.x, and .DELTA.y are needed in the digital functional logiccircuit to generate the phase shift. The nx and ny are position ofantenna element x, y and, in a currently preferred embodiment, has acorrespondence to the RF chain index from 0 to 15 within each circuitwhich controls 4.times.4 antenna elements within a frontend module. Fora circuit controlling 4.times.4 antenna element, nx and ny takes on thevalue from the set of [0, 1, 2, 3].

In some implementations, the RF traces for different frontend moduleshave equal length. In other implementations, the RF traces for differentfrontend modules have un-equal lengths. Some fixed phase correctionfactors .phi.X,Y are needed in the above equation to compensate for thetime delays .tau.X,Y introduced by the un-equal trace lengths. Note thatthese phase correction factors do not change with beam directions. Thephase correction factors, however, are proportional to the centerfrequency of the signal .phi.X,Y=fc*.tau.X,Y. Note that the two phasecorrection factors due to un-equal trace lengths can be absorbed into asingle correction factor .phi.X,Y+.phi.x,y=.DELTA..phi.X,Y,x,y.

A Quan[.] function is used to round-up the resulting arithmetic into thelength of phase shifter bits as well as the modulo operation. In anembodiment, the following operation is performed in parallel at alocation advantageously near to each antenna element:

1. Compute.DELTA..phi.X,Y,x,y+mx.DELTA.X+my.DELTA.Y+nx.DELTA.x+ny.DELTA.y usingmodulo 8 bit integer arithmetic (dropping carry bits)

2. Select 4 MSBs as the phase shifter value

A conventional method of implementing the phased array beamsteering isto compute the antenna phase shifts for every individual antenna elementin a single processor and distribute the antenna weight vectors (phasesand amplitudes) to each frontend module one by one. This would requiredissemination of Nx*Ny weight vectors to (Nx*Ny)/16 frontend moduleswhere each frontend module receives 16 antenna weight vectors.Conventional dissemination of weight vectors adds noise to the signalchannel and consumes area for routing of parallel buses which areproblems rather than solutions.

Note that with the computational mode where the computation of theantenna weight is done locally at each antenna element, the values formx, my, .DELTA.X, .DELTA.Y, .DELTA.x, and .DELTA.y are stored in thecommon registers and the .DELTA..phi.X,Y,x,y, nx and ny are stored inlocal registers. For each beam direction, only .DELTA.X, .DELTA.Y,.DELTA.x, and .DELTA.y need to be updated. The values for.DELTA..phi.X,Y,x,y, mx, my, nx and ny are written only once during theinitial configuration phase. This is significant reduction from theprior art method of updating which requires Nx*Ny antenna weight vectorsto be updated. Note also that there is no need to write .DELTA.X,.DELTA.Y, .DELTA.x, and .DELTA.y 16 times for each antenna elementwithin a frontend module.

Conclusion

The present invention is easily distinguished from conventional phasearray antennas by its serial bus coupling the processor to update allthe Phase-array transformation circuits at substantially the same time.A central idea of the invention is that when the array element placementon FIG. 6 (both in x and y directions) follows a regular pattern, theoperands for step 440 and 460 are the same for all modules (PhATcircuits). The apparatus updates all the phase shifter values by using“global write” to update these two operands to all PhAT circuitssubstantially simultaneously. Since these two operands are stored incommon register in a die, they are accessible to all the RF chains. Thisallows very fast update of the beam directions (by updating all phaseshifter values quickly) by using two global write operations.

Without the subject matter of the present application, conventionalsystems have to write to all the phase shifters individually. There areabout 768 phase shifters in a desired implementation. It would takeenormous amount of time to write the 768 phase shifters through serialbus. As a result, the beam direction update would be very slow.

It is a preferred embodiment to deploy a serial bus to reduce noise andto simplify the array implementation. Advantageously, the computationmode leads to faster update (fast beam steering).

A single chip antenna array control submodule is disclosed in thepresent patent application. The identical chip may be deployed over anantenna array with many elements. Only four operands need to bedistributed by the central control no matter how many antenna elementsor submodules are configured.

The present invention is easily distinguished from conventional phasedantenna array control by the substantially lower bandwidth requirementto distribute phase information into the shift circuits. Both lower datarates and higher phase data uploads are accomplished with less cost. Theinvention reduces bus speed or increases beam direction change rapidityor both.

The present invention is easily distinguished from conventional systemsby the characteristic of the RFIC to have central registers, localregisters, and common registers. Central registers are registers whichare located in central area controlling function at the central area.For example, the voltage reference source is in the central area whichprovides voltage reference or current bias to all local area. Localregisters are distributed to be physically close to their respectiveantenna element. When the common registers on each device receivescontent, it is duplicated to the local registers on the device. In thecompute mode of operation, phase is determined based on delta X anddelta Y locally using multiplier or recursive adder circuits. Wedesignate two common registers per device for delta X and delta Y whichare written to once for each device. The content is then duplicatedlocally on the same device, in an embodiment, 16 times when there are 16antenna elements. Advantageously, only a single bus needs to be routedwithin each semiconductor device which lowers area and routing resourceconsumption. This hierarchical structure is substantially advantageousover conventional many write operations to local registers.Advantageously, each device has a pin to control global vs individualoperations with the effect that 4 write operations can distribute deltaX, delta Y, delta′X and delta′Y to all the devices in the array. In thecompute mode, the address setting of each die position on the PCBenables indexing. In a tabulate mode of operation, a pointer isdistributed across the array by a global write of a pointer to a commonregister which updates a weight vector in a single write operation.

The present invention is easily distinguished from conventionalphased-array antennas by its method for transforming electrical signalsby determining antenna weight vectors for a series of beam directions atdigital functional logic circuits distributed among RFIC devicesadjacent to their associated phased-array antenna element: initializinglocal registers and common registers with integer-pair values forlocation of each antenna element in an phased-array antenna and a phasecorrection factor. For each desired beam direction in the series of beamdirections subsequent to initializing local registers and commonregisters, the method provides reading four binary coded phase shiftvalues from a serial bus; storing the four binary coded phase shiftvalues into common registers on each RFIC device accessible to eachdigital functional logic circuit associated with one of the phased-arrayantenna elements. At each digital functional logic circuit associatedwith one of the phased-array antenna elements, the method enablesdistributed computation by reading from common registers a pair ofbinary coded phase shift increment values for each increment in modulelocation on the printed circuit board and a pair of binary coded phaseshift increment values for each increment in antenna element location onthe module; reading from common registers integer-pair valuescorresponding to the location of the module on a printed circuit board;reading from common registers a phase correction factor; reading fromlocal registers associated with each digital functional logic circuitinteger-pair values corresponding to the coordinate location of itsassociated phased-array antenna element in the phased-array antenna on aradiating surface of the module; summing the phase correction factor andthe multiplication products of the four binary coded phase shift valueswith their corresponding location specific integer value; setting anantenna phase shift and amplitude weight value for its phased-arrayantenna element according to a resolution, in an embodiment, 4 bits; andtransforming the electrical signal according to the computed weightvalues. Advantageously, speed is improved, area and cost is reduced, andbandwidth is conserved over conventional systems by initializing localregisters and common registers by the following steps: writinginteger-pair values for m into common registers where m corresponds to acoordinate location of each module on a printed circuit board, in anembodiment, reading the integer-pair values from tie-up and tie-downcircuits at each mounting location on the printed circuit board; writinginteger-pair values for n into local registers where n corresponds to acoordinate location of an phased-array antenna element in thephased-array antenna on a radiating surface of the module, in anembodiment, reading the integer-pair values from a location on amounting surface of the module; and writing a binary coded value, withinthe range of 4 to 64 bits, in an embodiment 8 bits, for phase correctionfactor due to unequal trace lengths into local registers, in anembodiment, reading the binary coded value from a non-transitory storagedevice.

In an embodiment, the phase-array transformation circuit is electricallycoupled to a plurality of antenna elements embedded within a substrate.In an embodiment, the serial bus includes bus drivers to provide drivecapability. In an embodiments, the processor circuit is amicro-controller and in another embodiment a micro-processor. In anembodiment, the processor circuit has a plurality of serial busseswhereby the antenna element array can advantageously control a pluralityof antenna beams.

In an embodiment, the phase-array transformation circuit has a firstcommon register for the first operand coupled to a plurality of radiofrequency (RF) chains and a second common register for the secondoperand coupled to the plurality of RF chains whereby weights for eachelement of the antenna element array controlled by one of the pluralityof RF chains is advantageously re-computed after at most two globalwrite commands.

In an embodiment, each radio frequency (RF) chain of the plurality of RFchains transforms the first operand stored into the first commonregister and the second operand stored into the second common registerinto a phase weight and an amplitude weight suitable for its associatedelement of the antenna element array. In an embodiment, the radiofrequency (RF) chain has a digital multiplier and in an alternateembodiment, a recursive adder. In an embodiment, the antenna elementarray advantageously exhibit the antenna elements placed in a regularpattern embedded within a substrate which allows rapid recalculation ofthe antenna weights with only two global writes.

The techniques described herein can be implemented in digital electroniccircuitry, or in computer hardware, firmware, software, or incombinations of them. The techniques can be implemented as a computerprogram product, i.e., a computer program tangibly embodied in aninformation carrier, e.g., in a machine-readable storage device or in apropagated signal, for execution by, or to control the operation of,data processing apparatus, e.g., a programmable processor, a computer,or multiple computers. A computer program can be written in any form ofprogramming language, including compiled or interpreted languages, andit can be deployed in any form, including as a stand-alone program or asa module, component, subroutine, or other unit suitable for use in acomputing environment. A computer program can be deployed to be executedon one computer or on multiple computers at one site or distributedacross multiple sites and interconnected by a communication network.

Method steps of the techniques described herein can be performed by oneor more programmable processors executing a computer program to performfunctions of the invention by operating on input data and generatingoutput. Method steps can also be performed by, and apparatus of theinvention can be implemented as, special purpose logic circuitry, e.g.,an FPGA (field programmable gate array) or an ASIC (application-specificintegrated circuit). Modules can refer to portions of the computerprogram and/or the processor/special circuitry that implements thatfunctionality.

Processors suitable for the execution of a computer program include, byway of example, both general and special purpose microprocessors, andany one or more processors of any kind of digital computer. Generally, aprocessor will receive instructions and data from a read-only memory ora random access memory or both. The essential elements of a computer area processor for executing instructions and one or more memory devicesfor storing instructions and data. Generally, a computer will alsoinclude, or be operatively coupled to receive data from or transfer datato, or both, one or more mass storage devices for storing data, e.g.,magnetic, magneto-optical disks, or optical disks. Information carrierssuitable for embodying computer program instructions and data includeall forms of non-volatile memory, including by way of examplesemiconductor memory devices, e.g., EPROM, EEPROM, and flash memorydevices; magnetic disks, e.g., internal hard disks or removable disks;magneto-optical disks; and CD-ROM and DVD-ROM disks. The processor andthe memory can be supplemented by, or incorporated in special purposelogic circuitry. The special purpose logic circuit can incorporate astate machine implementation which provides the required control flowfor the operation.

A number of embodiments of the invention have been described.Nevertheless, it will be understood that various modifications may bemade without departing from the spirit and scope of the invention. Forexample, other serial bus protocols may be used. Accordingly, otherembodiments are within the scope of the following claims.

We claim:
 1. A system comprising: a processor circuit for control overan antenna element array by generation of an first operand and a firstglobal write command and a second operand and a second global writecommand; the processor coupled to a serial bus on a system printedcircuit board which conductively transmits operands and commands, theserial bus coupled to a plurality of phase-array transformation (PhAT)circuits, whereby the first operand is stored into each of the pluralityof PhAT circuits substantially simultaneously and the second operand isstored into each of the plurality of PhAT circuits substantiallysimultaneously wherein the operands are generated to direct a beamdirection.
 2. The system of claim 1 wherein the phase-arraytransformation circuit is electrically coupled to a plurality of antennaelements embedded within a substrate.
 3. The system of claim 1 whereinthe serial bus includes bus drivers to provide drive capability.
 4. Thesystem of claim 1 wherein the processor circuit is one of amicro-controller and a micro-processor.
 5. The system of claim 1 whereinthe processor circuit has a plurality of serial busses whereby theantenna element array can control a plurality of antenna beams.
 6. Thephase-array transformation circuit of claim 2 comprising: a first commonregister for the first operand; coupled to a plurality of radiofrequency (RF)chains; and a second common register for the secondoperand coupled to the plurality of RF chains, whereby weights for eachelement of the antenna element array controlled by one of the pluralityof RF chains is re-computed after at most two global write commands. 7.The phase-array transformation circuit of claim 6 wherein each radiofrequency (RF) chain of the plurality of RF chains transforms the firstoperand stored into the first common register and the second operandstored into the second common register into a phase weight and anamplitude weight suitable for its associated element of the antennaelement array.
 8. The radio frequency (RF) chain of claim 7 comprising adigital multiplier.
 9. A method for operation at a host processorcommunicatively coupled to a plurality of antenna array submodules, themethod comprising: determining a region that an antenna array ofsubmodules will be pointing next R+1; the host determining that theregion is adequately covered by one of a set of d phase weightspreviously associated with d directions for each element according to acontent addressable memory store device wherein the phase weights arecomputed using an element index and a Submodule index; and transmittingto each submodule an instruction to load a phase weight from thelocation d.
 10. The method of operation of claim 9 for controlling slaveRFIC devices in an antenna array further comprising: initializing at thesame time all common registers within every slave RFIC device in theantenna array to the same calibrated gain values; transferring saidcalibrated gain values into every instance of local registers fortransformation by antenna element specific phase shifter factors;storing antenna element specific phase shifter factors in localregisters; computing phase shifter values; and looking up gain settings.